How UVM RAL works? - The Art of Verification (2022)

Today let’s talk about UVM RAL. In this post, I will introduce – What is RAL? and Why RAL is needed? and How the UVM RAL structure looks like?

We know that our DUT (be it an SoC or Subsystem or Design Block) contains a number of different types of registers e.g. control registers, status registers. Most likely these registers are contained within a dedicated block called CSR Block aka “Control and Status Register” Block. But the name could be different in different SoCs. These registers are arranged inside the CSR block based on the address map in the SoC or Subsystem. Both hardware and software need to access control registers to program and control different functionalities in the Chip/Subsystem/Block. Similarly, Status registers are read to know the status of an operation, for example, Interrupt assertion after completion of certain functionality, that means when a certain task is completed by the design, it sets a particular bit/s of the register field to indicate the completion of the operation. e.g. data transfer completion.

To understand RAL, I would recommend you, first and foremost get familiar with the Hardware Registers, if not having already, – I mean, How the registers are defined, what are different types, what are different fields and attributes?

The UVM register layer acts similarly by modeling and abstracting registers of a design. It attempts to mirror the design registers by creating a model in the verification testbench. By applying stimulus to the register model, the actual design registers will exhibit the changes applied by the stimulus.

(Video) Easier UVM - Register Layer

The benefit of this approach comes from the high level of abstraction provided. The bus protocols for accessing registers can change from design to design, but any stimulus developed for verification of the registers doesn’t have to. This makes it easy to port code from one project to the next if the registers are the same. Taking a look at below provides a better understanding of what a register model implementation might look like with respect to the UVM environment.

How UVM RAL works? - The Art of Verification (1)

One thing that is interesting about the above figure is the ‘Generator’ bubble. Modern designs have hundreds if not thousands of registers and tens of thousands of register fields. Manually trying to write SystemVerilog code to represent those thousands of registers and register fields would be a gruesome task. This is where generators come into play. A generator’s job is to take the register specifications of a design (usually in the form of a spreadsheet) and automatically ‘generate’ the equivalent register model in SystemVerilog code. In order to use generators or even understand their output, one should first have a good grasp of the UVM register layer.

How exactly does the register layer work?

First, the register model is built using an organized hierarchical structure. The structure incorporates memory, registers, and address maps into address blocks. Ultimately the blocks communicate with an adapter and receive updates from a predictor, both of which interact with the rest of the verification environment. Once the structure is built, register access API is used to send signals to the DUT where a monitor will report back any information to the register model for the purposes of synchronization.

(Video) What is UVM Register Modeling?

Register Layer Structure

Each register has its own class and each field belonging to the register is created and configured within the class.

class my_register_class extends uvm_reg; `uvm_object_utils(my_register_class) //Register the register with the factory rand uvm_reg_field my_register_field; //Declaring register field //Constructor //.name = Name of the register //.n_bits = Number of bits in the register //.has_coverage = Coverage of the register function new(string name = "my_register_class"); super.new(.name(name), .n_bits(0), .has_coverage(UVM_NO_COVERAGE)); endfunction : new //Build Function virtual function void build(); //Create the register field and assign the handle to it my_register_field = uvm_reg_field::type_id::create("my_register_field"); my_register_field.configure(.parent (this), //parent .size (0), //# bits of the field .lsb_pos (0), // LSB position .access ("WO"), //Accessibility to write only .volatile (0), //Volatility, Can DUT change this value? .reset (0), //Value in reset .has_reset (1), // Can the field be reset? .is_rand (1), //Can the values be randomized? .individually_accesible (1) //Does the field occupy by entire byte lane? ); endfunction : buildendclass : my_register_class

Registers are then organized into blocks where a register map is also declared. The register map organizes the registers according to their designated addresses. These blocks are then instantiated in a uvm_environment or the uvm_test depending on preference.

class my_register_block extends uvm_reg_block; `uvm_object_utils(my_register_block) //Register with the factory rand my_register_class my_register; //Register handle uvm_reg_map my_reg_map; //Register map //Constructor //.name = Name of the register //.has_coverage = Coverage of the register function new(string name = "my_register_block"); super.new(.name(name), .has_coverage(UVM_NO_COVERAGE)); endfunction : new //Build Function virtual function void build(); my_register = my_register_class::type_id::create("my_register"); //Create the register my_register.configure(.blk_parent (this)); //parent block my_register.build(); //Build the register fields my_reg_map = create_map(.name (my_reg_map), //create register map .base_addr (8'h00), //offset from the base address .n_byetes (1), //Byte width of the address .endian (UVM_LITTLE_ENDIAN)); //Endianness my_reg_map.add_reg(.rg (my_register), //register instance .offset (8'h00), //offset from the base address .rights ("WO")); //Write Only lock_model(); //lock endfunction : build endclass : my_register_class

Up next is the creation of an adapter in the agent. The adapter is what makes abstraction possible. It acts as a bridge between the model and the lower levels. Its function is twofold: it must convert register model transactions to the lower level bus transactions and it must convert any lower-level bus transactions to register model transactions.

class my_register_adapter extends uvm_reg_adapter; `uvm_object_utils(my_register_adapter) //Register with the factory //Constructor function new(string name = ""); super.new(name); endfunction : new //Build Function virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); my_transaction_class my transaction = my_transaction_class::type_id::create("my_transaction"); my_transaction.my_register_field = rw.data; return my_transaction; endfunction : reg2bus virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); my_transaction_class my transaction; if(! $cast (my_transaction, bus_item)) begin `uvm_fatal("BUS_ITEM_ERROR", "bus_item cannot be converted to my_transaction") end rw.kind = UVM_WRITE; rw.data = my_transaction.my_register_field; rw.status = UVM_IS_OK; return; endfunction : bus2reg endclass : my_register_adapter

The predictor receives information from the monitor such that changes in values in the registers of the DUT are passed back to the register model.

(Video) Webinar | Introduction to the UVM Register Layer

typedef uvm_reg_predictor#(my_transaction_class) my_reg_predictor;

uvm_reg_predictor parameterized with the my_transaction_class

Eventually, the structure that is created looks similar to the diagram, below.

How UVM RAL works? - The Art of Verification (2)

Until now, only registers have been considered, but the register layer also allows memory to be modeled as well. You can see from the image above a memory module is represented in the model, but that discussion is for another time.

(Video) Introduction to SV-UVM RAL(Register Abstraction Layer).

Now that the structure has been described; how do we generate stimulus?

Register access is dictated by the register API. Methods, like write() and read() called from a sequence, will send data through the register model to the sequencer, then the driver, and ultimately to the DUT. The monitor picks up any activity and sends it back to the predictor, at which point the predictor will send the data to the adapter where the bus data is converted to a register model format for the register model value to be updated through a predict() method call.

WRITE

virtual task write( output uvm_status_e status, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0)

READ

virtual task read( output uvm_status_e status, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0)
class my_register_sequence extends uvm_reg_sequence; `uvm_object_utils(my_register_sequence) //Register with the factory my_register_block block; //Constructor function new(string name = ""); super.new(name); endfunction : new //Build Function virtual task body(); uvm_status_e status; int data = 42; block.my_register.write(.status(status), .value(value), .path(UVM_FRONTDOOR). .parent(this)); block.my_register.read(.status(status), .value(value), .path(UVM_FRONTDOOR). .parent(this)); endtask : body endclass : my_register_sequence

A sequence is created to call the API (write() and read()) which will cause movement of data.

Sequences are built to house any register access method calls. The block is declared (notice it does not have to call the create() method) and the registers are referenced hierarchically in the body task to call write() and read(). There also exists peek() and poke() which are utilized for individual field accesses. Many other register access methods exist, including: mirror(), get(), set(), reset(), and more.

(Video) Why do we need UVM Register Abstraction Layer?

Obviously, not everything about the UVM register layer is explicitly talked about here, but I tried to provide an overall idea of what the register layer is and how it’s used so that getting started won’t be so intimidating. There are plenty of examples out there. In order to really get to know the register layer, tons of additional reading, examples browsing, and actual practice have to be done.

I believe, you enjoyed this post! If yes, keep posting your comments, so that I got to know your views. Till next post, stay safe and healthy! Take care, see you again soon with a new post !! Keep on learning, Keep on growing !!

FAQs

How UVM RAL works? - The Art of Verification? ›

The UVM register layer acts similarly by modeling and abstracting registers of a design. It attempts to mirror the design registers by creating a model in the verification testbench. By applying stimulus to the register model, the actual design registers will exhibit the changes applied by the stimulus.

How does UVM RAL work? ›

UVM RAL as the name suggests, is a high-level object-oriented abstraction layer to access design registers. RAL model mimics the design registers and this entire model is fully configurable. Due to its abstraction behavior, RAL model can be easily migrated from block level to system level.

What are desired and mirrored values in RAL? ›

By definition, desired value is function of testbench set value, mirrored value and access policy. For RW policy, desired value is same as testbench set value i.e. mirrored value is irrelevant whereas for RO policy desired value is same as mirrored value i.e. testbench set value is irrelevant.

What is register model in UVM? ›

A register model is an entity that encompasses and describes the hierarchical structure of class objects for each register and its individual fields. We can perform read and write operations on the design using a register model object.

What is backdoor access in UVM? ›

What are backdoor accesses ? UVM also allows backdoor accesses which uses a simulator database to directly access the signals within the DUT. Write operations deposit a value onto the signal and read operations sample the current value from the register signal.

What is UVM based verification? ›

The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001.

What are the advantages of the UVM RAL model? ›

The advantages of UVM RAL Model are, Provides high-level abstraction for reading and writing DUT registers. i.e, registers can be accessed with its names. UVM provides a register test sequence library containing predefined test cases these can be used to verify the registers and memories.

Is UVM is independent of Systemverilog? ›

Is Uvm Is Independent Of Systemverilog? Answer : UVM is a methodology based on Systemverilog language and is not a language on its own.

What is mirror in UVM? ›

1) Mirror compares read value against the mirror value. However, with set_check_on_read(1) method, we can eliminate this difference. 2) Read, reads DUT value and returns it to the caller. Mirror also reads DUT value but does not return the value to the caller.

What is the difference between Create and new in UVM? ›

create() is factory construction. You are delegating new() to the factory - the factory looks for overrides and replaces construction of your class with some other derived class. You should always use create() rather than using new() for classes registered with the factory.

What is factory override in UVM? ›

UVM factory is a mechanism to improve flexibility and scalability of the testbench by allowing the user to substitute an existing class object by any of its inherited child class objects.

What is an objection in UVM? ›

What is an objection mechanism in UVM? Objection mechanism is a UVM strategy used to decide the end of test. There are number of zero time consuming phases before and after the run_phase. The run_phase is the only time consuming phase which is run in parallel for all the components.

What is UVM testbench? ›

All verification components, interfaces and DUT are instantiated in a top level module called testbench. It is a static container to hold everything required to be simulated and becomes the root node in the hierarchy. This is usually named tb or tb_top although it can assume any other name.

What are UVM phases? ›

UVM Phases are predefined virtual function / tasks defined in UVM component which are supposed to be populated by classes extending from UVM component. These pre-defined virtual methods give each class (extended from UVM component) in the TB a common understanding of what should be executed in each phase.

How do you use UVM? ›

UVM-1: UVM Basics | Synopsys - YouTube

What is bit bash test? ›

Verify the implementation of a single register by attempting to write 1's and 0's to every bit in it, via every address map in which the register is mapped, making sure that the resulting value matches the mirrored value.

Is UVM a functional verification? ›

Universal Verification Methodology (UVM) is the industry standard for functional verification methodology developed by key EDA vendors and industry leaders. It uses a SystemVerilog-based, OOP-centric approach to improve interoperability and code reusability.

Why is UVM used? ›

The idea behind UVM is to enhance flexibility and reuse code so that the same testbench can be configured in different ways to build different components, and provide different stimulus. These new user defined configuration classes are recommended to be derived from uvm_object .

What is special about UVM? ›

1. UVM is home to world-class scholars who love to teach. At UVM, 98 percent of classes are taught by full-time faculty (with two percent taught by graduate students). That means you'll learn from and be advised by world-class researchers, who often choose UVM as their home for its emphasis on undergraduate teaching.

What is SystemVerilog used for? ›

SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard.

What is CSR in UVM? ›

We know that our DUT (be it a SoC or Subsystem or Design Block) contains number of different type of registers e.g. control registers, status registers. Most likely these registers are contained within a dedicated block called CSR Block aka “Control and Status Register” Block.

What is the difference between UVM and SystemVerilog? ›

SystemVerilog classes allow Object Orientated Programming (OOP) techniques to be applied to testbenches. The UVM itself is a library of base classes which facilitate the creation of structured testbenches. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation.

What is advantage of SV with UVM? ›

Configuration mechanism: It simplify configuration of objects with deep hierarchy. The configuration mechanism helps in easily configuring different testbench components based upon verification environment using it, and without worrying about how deep any component is in the testbench hierarchy.

Is UVM open source? ›

UVM is in the picture

No open source ASIC design toolkit can be complete without support for Universal Verification Methodology, or UVM, which is one of the most widespread verification methodologies for large-scale ASIC design.

What is Uvm_reg_block? ›

Block abstraction base class. A block represents a design hierarchy. It can contain registers, register files, memories and sub-blocks. A block has one or more address maps, each corresponding to a physical interface on the block.

How do you start a sequence in UVM? ›

Logic to generate and send the sequence_item will be written inside the body() method of the sequence. The handshake between the sequence, sequencer and driver to send the sequence_item is given below.
...
Starting The Sequence:
Method CallDescription
req.randomize()This method is to randomize the sequence_item
6 more rows

What is the difference between copy and clone in UVM? ›

clone method works exactly the same as a copy method, the difference being that a clone will return an object with the copied contents. So this saves some trouble of creating the second object before copy.

What is quasi static in UVM? ›

Quasi-static means that at a given instant in time we can assume the problem is static. This assumption works well when inertial effects are very low.

What is the difference between object and component in UVM? ›

Uvm_objects doesn't have build phase, components have it. All that is built in build phase exists from the start of the simulation until the end of simulation. Uvm_objects doesn't have "parent" argument in the super.

What is the difference between instance override and type override? ›

I think, you can do type override when you want to replace all the instances where a particular class is used. But when you need to override one particular instance of a class then you can use override by instance.

Why do we need constructor in UVM? ›

By default the constructor new() will create the class object (i.e., allocate space for all the properties/methods in the memory). Often new(), is also used to initialize the properties of the class object.

What is TLM port in UVM? ›

The TLM Port is used to send the transactions. TLM Ports has unidirectional and bidirectional ports. A port can be connected to any compatible port, export, or imp port.

How do you track objections in UVM? ›

Tracing of objection activity can be turned on to follow the activity of the objection mechanism. It may be turned on for a specific objection instance with uvm_objection::trace_mode, or it can be set for all objections from the command line using the option +UVM_OBJECTION_TRACE.

Why we need raise and drop objection in UVM? ›

Basically, if there are no objections raised, the simulation stops. So, when you comment out your code that raises and drops objections, no objections are raised, so the simulation stops immediately (without doing anything).

What is drain time in UVM? ›

Drain time is the period between the last objection to ending a phase, and the actual time the phase is terminated. It usually represents the time it takes for your last set of stimulus (a sequence) to propagate through your design and its output to be captured by a monitor.

How is UVM testbench initiated? ›

A test is usually started within testbench top by a task called run_test . This global task should be supplied with the name of user-defined UVM test that needs to be started. If the argument to run_test is blank, it is necessary to specify the testname via command-line options to the simulator using +UVM_TESTNAME .

What is a UVM agent? ›

An agent is a container that holds and connects the driver, monitor, and sequencer instances. The agent develops a structured hierarchy based on the protocol or interface requirement.

What is constrained random verification? ›

Constrained Random Verification (CRV) is a methodology that is supported by SystemVerilog which has a built-in constraint solver. This allows you to constraint your stimulus to better target a design function, thereby allowing you to reach your coverage goal faster with accuracy.

How UVM phasing is triggered? ›

It is usually called from within an initial block in the top level module of the Testbench. Once the run_test() method is called, it constructs the root component of the UVM environment & then triggers/initiates the UVM Phasing process.

Why final phase is top down in UVM? ›

The final phase is also top down since all the testcases and the stimulus related procedures ends here and it is the final stage before exit. Hence it is being used to check for the final adjustment or loopback is needed or not before exit.

What is UVM in semiconductor? ›

The Universal Verification Methodology (UVM) is an open source SystemVerilog library allowing creation of reusable verification components and assembling test environments utilizing constrained random stimulus generation and functional coverage methodologies.

Who uses UVM? ›

UVM is mainly derived from Open Verification Methodology (OVM) and is supported by multiple EDA vendors like Synopsys, Cadence, Mentor and Aldec.

Why do we need virtual sequencer in UVM? ›

The need for a virtual sequence arises when you require different sequences to be run on different environments. For example, an SoC design might have multiple different interfaces that might need to be driven by a different set of sequences on individual sequencers.

What is bats script? ›

Bats is a TAP-compliant testing framework for Bash. It provides a simple way to verify that the UNIX programs you write behave as expected. A Bats test file is a Bash script with special syntax for defining test cases. Under the hood, each test case is just a function with a description.

What is bash used for? ›

What is Bash? In short, Bash is the Unix command-line interface (CLI). You'll also see it called the terminal, the command line, or the shell. It's a command language that allows us to work with files on our computers in a way that's far more efficient and powerful than using a GUI (graphical user interface).

How do I test a Unix shell script? ›

On Unix-like operating systems, the test command checks file types and compares values.
...
Expressions.
( EXPRESSION )EXPRESSION is true
-b FILEFILE exists and is block special
-c FILEFILE exists and is character special
-d FILEFILE exists and is a directory
-e FILEFILE exists
32 more rows
Nov 6, 2021

How do you use UVM? ›

UVM-1: UVM Basics | Synopsys - YouTube

What are UVM phases? ›

UVM Phases are predefined virtual function / tasks defined in UVM component which are supposed to be populated by classes extending from UVM component. These pre-defined virtual methods give each class (extended from UVM component) in the TB a common understanding of what should be executed in each phase.

How do you start a sequence in UVM? ›

Logic to generate and send the sequence_item will be written inside the body() method of the sequence. The handshake between the sequence, sequencer and driver to send the sequence_item is given below.
...
Starting The Sequence:
Method CallDescription
req.randomize()This method is to randomize the sequence_item
6 more rows

Is UVM a functional verification? ›

Universal Verification Methodology (UVM) is the industry standard for functional verification methodology developed by key EDA vendors and industry leaders. It uses a SystemVerilog-based, OOP-centric approach to improve interoperability and code reusability.

Why is UVM used? ›

The idea behind UVM is to enhance flexibility and reuse code so that the same testbench can be configured in different ways to build different components, and provide different stimulus. These new user defined configuration classes are recommended to be derived from uvm_object .

What is special about UVM? ›

1. UVM is home to world-class scholars who love to teach. At UVM, 98 percent of classes are taught by full-time faculty (with two percent taught by graduate students). That means you'll learn from and be advised by world-class researchers, who often choose UVM as their home for its emphasis on undergraduate teaching.

Videos

1. UVM- Universal Verification Methodology- Sequence_item - Part1
(Meghana Shanthappa)
2. UVM RAL (Register model) Demo session
(VLSIGuru Training Institute)
3. DVinsight – Design Verification Editor Checker for SV/UVM
(Agnisys Inc.)
4. UVM Session 5 (Design & Verification of JK flip-flop)
(Electronics & VLSI Projects)
5. Overview Of Prediction Modes In UVM Register Modelling
(Cadence Design Systems)
6. UVM-1: UVM Basics | Synopsys
(Synopsys)

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